In recent years, the influence of component irregularities, crosstalk, IR-drop, etc., has been increasing as processing becomes more refined, leading to a large discrepancy between path delay at the stage of a design process (predicted delay) and path delay on a manufactured chip (actual delay). If the discrepancy between the path delays becomes so large that a chip cannot satisfy a target operation frequency (specification) during a chip inspection process, a setback in the design process results.
In the inspection process, a delay test is carried out to confirm whether the chip satisfies the target operation frequency. In the delay test, a test pattern (test vector) is successively input twice to the chip to confirm the operation of the chip. In the delay test, specifically, the cycle of successive inputs of test patterns is shortened stepwise, and the cycle immediately before the point at which the chip becomes incapable of normal operation is identified to confirm whether the identified cycle satisfies a target cycle (frequency).
If the chip does not satisfy the target operation frequency, failure diagnosis is carried out to identify the location or cause of the failure, and a return to the design process is made. Failure diagnosis is carried out using the path delay of each of paths in the chip. According to conventional failure diagnosis, a path having a large predicted path delay estimated by static timing analysis (STA), statistical static timing analysis (SSTA), etc., is presumed to be a failure-causing path.
According to conventional failure diagnosis, a measured value obtained via a test pattern is assigned to a path presumed to be a failure-causing path and speed path analysis, etc. is performed to identify, in detail, the cause of failure. The measured value obtained from a test pattern is equivalent to the delay value immediately before the point of failure, i.e., the smallest interval at which two test patterns can be input to the chip and still yield output values that match expected values (see, for example, Japanese Laid-Open Patent Publication Nos. 2003-43115 and 2005-83895).
According to the conventional technique, however, if multiple paths are activated (propagate signals) simultaneously when a test pattern is input to the chip, precisely determining the failure-causing path is difficult, which leads to a problem of reduced reliability of the failure diagnosis.
Specifically, because a discrepancy exists between the predicted path delay and the actual path delay, a path with a large predicted path delay (e.g., greatest predicted delay) does not always determine the measured value obtained via a test pattern when multiple paths are activated. For this reason, if a path determining the measured value obtained via a test pattern is presumed simply from the predicted path delay, the accuracy of failure diagnosis deteriorates.